wafer.space Community - How we can do the same here, excluding

4:00 p.m.

You need to set SYNTH_EXCLUDED_CELL_FILE to point to your exclude file.

4:01 p.m.

You can find the current one in gf180mcu/gf180mcuD/libs.tech/librelane/gf180mcu_fd_sc_mcu7t5v0/synth_exclude.cells

1

it is possible to overlay it?

4:03 p.m.

I don't want to touch the gf180mcu repo

No, unfortunately not. Make a copy of the file in your repository and add the line.

1

Yes, that's what I did

4:07 p.m.

But it'd be really nice to understand the actual issue

But if they are changes in gf180mcu you will not recognize

4:09 p.m.

Today you know, but not tomorrow

Yes, the proper solution is to fix the simulation model of the cell (if that is the issue).

$ cat 06-yosys-synthesis/chip_top.nl.v | grep gf180mcu_fd_sc_mcu7t5v0__oai21_1 | wc -l 0 lolo (edited)

Leo Moser (mole99)

Yes, the proper solution is to fix the simulation model of the cell (if that is the issue).

There's a good chance the simulation model is not the issue, since there are many gf180mcu_fd_sc_mcu7t5v0__oai21_2 instances in the design that does pass the GL tests

urish

There's a good chance the simulation model is not the issue, since there are many gf180mcu_fd_sc_mcu7t5v0__oai21_2 instances in the design that does pass the GL tests

what is the issue then?

10:32 p.m.

yosys?